/**
 * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
 *
 *  SPDX-License-Identifier: Apache-2.0 OR MIT
 */
#pragma once

#include <stdint.h>
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif

/** LP_AONCLKRST_ROOT_CLK_CONF_REG register
 *  need_des
 */
#define LP_AONCLKRST_ROOT_CLK_CONF_REG (DR_REG_LP_AONCLKRST_BASE + 0x0)
/** LP_AONCLKRST_SLOW_CLK_SEL : R/W; bitpos: [25:23]; default: 0;
 *  need_des
 */
#define LP_AONCLKRST_SLOW_CLK_SEL    0x00000007U
#define LP_AONCLKRST_SLOW_CLK_SEL_M  (LP_AONCLKRST_SLOW_CLK_SEL_V << LP_AONCLKRST_SLOW_CLK_SEL_S)
#define LP_AONCLKRST_SLOW_CLK_SEL_V  0x00000007U
#define LP_AONCLKRST_SLOW_CLK_SEL_S  23
/** LP_AONCLKRST_FAST_CLK_SEL : R/W; bitpos: [27:26]; default: 1;
 *  need_des
 */
#define LP_AONCLKRST_FAST_CLK_SEL    0x00000003U
#define LP_AONCLKRST_FAST_CLK_SEL_M  (LP_AONCLKRST_FAST_CLK_SEL_V << LP_AONCLKRST_FAST_CLK_SEL_S)
#define LP_AONCLKRST_FAST_CLK_SEL_V  0x00000003U
#define LP_AONCLKRST_FAST_CLK_SEL_S  26
/** LP_AONCLKRST_PLL80M_CLK_FORCE_ON : R/W; bitpos: [28]; default: 0;
 *  need_des
 */
#define LP_AONCLKRST_PLL80M_CLK_FORCE_ON    (BIT(28))
#define LP_AONCLKRST_PLL80M_CLK_FORCE_ON_M  (LP_AONCLKRST_PLL80M_CLK_FORCE_ON_V << LP_AONCLKRST_PLL80M_CLK_FORCE_ON_S)
#define LP_AONCLKRST_PLL80M_CLK_FORCE_ON_V  0x00000001U
#define LP_AONCLKRST_PLL80M_CLK_FORCE_ON_S  28
/** LP_AONCLKRST_XTAL_CLK_FORCE_ON : R/W; bitpos: [29]; default: 0;
 *  need_des
 */
#define LP_AONCLKRST_XTAL_CLK_FORCE_ON    (BIT(29))
#define LP_AONCLKRST_XTAL_CLK_FORCE_ON_M  (LP_AONCLKRST_XTAL_CLK_FORCE_ON_V << LP_AONCLKRST_XTAL_CLK_FORCE_ON_S)
#define LP_AONCLKRST_XTAL_CLK_FORCE_ON_V  0x00000001U
#define LP_AONCLKRST_XTAL_CLK_FORCE_ON_S  29
/** LP_AONCLKRST_FOSC_CLK_FORCE_ON : R/W; bitpos: [30]; default: 0;
 *  need_des
 */
#define LP_AONCLKRST_FOSC_CLK_FORCE_ON    (BIT(30))
#define LP_AONCLKRST_FOSC_CLK_FORCE_ON_M  (LP_AONCLKRST_FOSC_CLK_FORCE_ON_V << LP_AONCLKRST_FOSC_CLK_FORCE_ON_S)
#define LP_AONCLKRST_FOSC_CLK_FORCE_ON_V  0x00000001U
#define LP_AONCLKRST_FOSC_CLK_FORCE_ON_S  30
/** LP_AONCLKRST_ANA_SEL_REF_PLL8M : R/W; bitpos: [31]; default: 0;
 *  need_des
 */
#define LP_AONCLKRST_ANA_SEL_REF_PLL8M    (BIT(31))
#define LP_AONCLKRST_ANA_SEL_REF_PLL8M_M  (LP_AONCLKRST_ANA_SEL_REF_PLL8M_V << LP_AONCLKRST_ANA_SEL_REF_PLL8M_S)
#define LP_AONCLKRST_ANA_SEL_REF_PLL8M_V  0x00000001U
#define LP_AONCLKRST_ANA_SEL_REF_PLL8M_S  31

/** LP_AONCLKRST_LP_CLK_PO_EN_REG register
 *  need_des
 */
#define LP_AONCLKRST_LP_CLK_PO_EN_REG (DR_REG_LP_AONCLKRST_BASE + 0x4)
/** LP_AONCLKRST_CLK_CORE_EFUSE_OEN : R/W; bitpos: [0]; default: 0;
 *  need_des
 */
#define LP_AONCLKRST_CLK_CORE_EFUSE_OEN    (BIT(0))
#define LP_AONCLKRST_CLK_CORE_EFUSE_OEN_M  (LP_AONCLKRST_CLK_CORE_EFUSE_OEN_V << LP_AONCLKRST_CLK_CORE_EFUSE_OEN_S)
#define LP_AONCLKRST_CLK_CORE_EFUSE_OEN_V  0x00000001U
#define LP_AONCLKRST_CLK_CORE_EFUSE_OEN_S  0
/** LP_AONCLKRST_CLK_LP_BUS_OEN : R/W; bitpos: [1]; default: 0;
 *  need_des
 */
#define LP_AONCLKRST_CLK_LP_BUS_OEN    (BIT(1))
#define LP_AONCLKRST_CLK_LP_BUS_OEN_M  (LP_AONCLKRST_CLK_LP_BUS_OEN_V << LP_AONCLKRST_CLK_LP_BUS_OEN_S)
#define LP_AONCLKRST_CLK_LP_BUS_OEN_V  0x00000001U
#define LP_AONCLKRST_CLK_LP_BUS_OEN_S  1
/** LP_AONCLKRST_CLK_AON_SLOW_OEN : R/W; bitpos: [2]; default: 0;
 *  need_des
 */
#define LP_AONCLKRST_CLK_AON_SLOW_OEN    (BIT(2))
#define LP_AONCLKRST_CLK_AON_SLOW_OEN_M  (LP_AONCLKRST_CLK_AON_SLOW_OEN_V << LP_AONCLKRST_CLK_AON_SLOW_OEN_S)
#define LP_AONCLKRST_CLK_AON_SLOW_OEN_V  0x00000001U
#define LP_AONCLKRST_CLK_AON_SLOW_OEN_S  2
/** LP_AONCLKRST_CLK_AON_FAST_OEN : R/W; bitpos: [3]; default: 0;
 *  need_des
 */
#define LP_AONCLKRST_CLK_AON_FAST_OEN    (BIT(3))
#define LP_AONCLKRST_CLK_AON_FAST_OEN_M  (LP_AONCLKRST_CLK_AON_FAST_OEN_V << LP_AONCLKRST_CLK_AON_FAST_OEN_S)
#define LP_AONCLKRST_CLK_AON_FAST_OEN_V  0x00000001U
#define LP_AONCLKRST_CLK_AON_FAST_OEN_S  3
/** LP_AONCLKRST_CLK_SLOW_OEN : R/W; bitpos: [4]; default: 0;
 *  need_des
 */
#define LP_AONCLKRST_CLK_SLOW_OEN    (BIT(4))
#define LP_AONCLKRST_CLK_SLOW_OEN_M  (LP_AONCLKRST_CLK_SLOW_OEN_V << LP_AONCLKRST_CLK_SLOW_OEN_S)
#define LP_AONCLKRST_CLK_SLOW_OEN_V  0x00000001U
#define LP_AONCLKRST_CLK_SLOW_OEN_S  4
/** LP_AONCLKRST_CLK_FAST_OEN : R/W; bitpos: [5]; default: 0;
 *  need_des
 */
#define LP_AONCLKRST_CLK_FAST_OEN    (BIT(5))
#define LP_AONCLKRST_CLK_FAST_OEN_M  (LP_AONCLKRST_CLK_FAST_OEN_V << LP_AONCLKRST_CLK_FAST_OEN_S)
#define LP_AONCLKRST_CLK_FAST_OEN_V  0x00000001U
#define LP_AONCLKRST_CLK_FAST_OEN_S  5
/** LP_AONCLKRST_CLK_FOSC_OEN : R/W; bitpos: [6]; default: 0;
 *  need_des
 */
#define LP_AONCLKRST_CLK_FOSC_OEN    (BIT(6))
#define LP_AONCLKRST_CLK_FOSC_OEN_M  (LP_AONCLKRST_CLK_FOSC_OEN_V << LP_AONCLKRST_CLK_FOSC_OEN_S)
#define LP_AONCLKRST_CLK_FOSC_OEN_V  0x00000001U
#define LP_AONCLKRST_CLK_FOSC_OEN_S  6
/** LP_AONCLKRST_CLK_RC32K_OEN : R/W; bitpos: [7]; default: 0;
 *  need_des
 */
#define LP_AONCLKRST_CLK_RC32K_OEN    (BIT(7))
#define LP_AONCLKRST_CLK_RC32K_OEN_M  (LP_AONCLKRST_CLK_RC32K_OEN_V << LP_AONCLKRST_CLK_RC32K_OEN_S)
#define LP_AONCLKRST_CLK_RC32K_OEN_V  0x00000001U
#define LP_AONCLKRST_CLK_RC32K_OEN_S  7
/** LP_AONCLKRST_CLK_SXTAL_OEN : R/W; bitpos: [8]; default: 0;
 *  need_des
 */
#define LP_AONCLKRST_CLK_SXTAL_OEN    (BIT(8))
#define LP_AONCLKRST_CLK_SXTAL_OEN_M  (LP_AONCLKRST_CLK_SXTAL_OEN_V << LP_AONCLKRST_CLK_SXTAL_OEN_S)
#define LP_AONCLKRST_CLK_SXTAL_OEN_V  0x00000001U
#define LP_AONCLKRST_CLK_SXTAL_OEN_S  8
/** LP_AONCLKRST_CLK_SOSC_OEN : R/W; bitpos: [9]; default: 0;
 *  1'b1: probe sosc clk on
 *  1'b0: probe sosc clk off
 */
#define LP_AONCLKRST_CLK_SOSC_OEN    (BIT(9))
#define LP_AONCLKRST_CLK_SOSC_OEN_M  (LP_AONCLKRST_CLK_SOSC_OEN_V << LP_AONCLKRST_CLK_SOSC_OEN_S)
#define LP_AONCLKRST_CLK_SOSC_OEN_V  0x00000001U
#define LP_AONCLKRST_CLK_SOSC_OEN_S  9

/** LP_AONCLKRST_MISC_REG register
 *  need_des
 */
#define LP_AONCLKRST_MISC_REG (DR_REG_LP_AONCLKRST_BASE + 0x8)
/** LP_AONCLKRST_ETM_EVENT_TICK_EN : R/W; bitpos: [31]; default: 0;
 *  need_des
 */
#define LP_AONCLKRST_ETM_EVENT_TICK_EN    (BIT(31))
#define LP_AONCLKRST_ETM_EVENT_TICK_EN_M  (LP_AONCLKRST_ETM_EVENT_TICK_EN_V << LP_AONCLKRST_ETM_EVENT_TICK_EN_S)
#define LP_AONCLKRST_ETM_EVENT_TICK_EN_V  0x00000001U
#define LP_AONCLKRST_ETM_EVENT_TICK_EN_S  31

/** LP_AONCLKRST_TIMER_REG register
 *  need_des
 */
#define LP_AONCLKRST_TIMER_REG (DR_REG_LP_AONCLKRST_BASE + 0xc)
/** LP_AONCLKRST_LP_TIMER_RST_EN : R/W; bitpos: [31]; default: 0;
 *  need_des
 */
#define LP_AONCLKRST_LP_TIMER_RST_EN    (BIT(31))
#define LP_AONCLKRST_LP_TIMER_RST_EN_M  (LP_AONCLKRST_LP_TIMER_RST_EN_V << LP_AONCLKRST_LP_TIMER_RST_EN_S)
#define LP_AONCLKRST_LP_TIMER_RST_EN_V  0x00000001U
#define LP_AONCLKRST_LP_TIMER_RST_EN_S  31

/** LP_AONCLKRST_WDT_REG register
 *  need_des
 */
#define LP_AONCLKRST_WDT_REG (DR_REG_LP_AONCLKRST_BASE + 0x10)
/** LP_AONCLKRST_LP_WDT_RST_EN : R/W; bitpos: [31]; default: 0;
 *  need_des
 */
#define LP_AONCLKRST_LP_WDT_RST_EN    (BIT(31))
#define LP_AONCLKRST_LP_WDT_RST_EN_M  (LP_AONCLKRST_LP_WDT_RST_EN_V << LP_AONCLKRST_LP_WDT_RST_EN_S)
#define LP_AONCLKRST_LP_WDT_RST_EN_V  0x00000001U
#define LP_AONCLKRST_LP_WDT_RST_EN_S  31

/** LP_AONCLKRST_CLOCKCALI_REG register
 *  need_des
 */
#define LP_AONCLKRST_CLOCKCALI_REG (DR_REG_LP_AONCLKRST_BASE + 0x14)
/** LP_AONCLKRST_LP_CLK_CALI_XTAL_FORCE_ON : R/W; bitpos: [29]; default: 0;
 *  need_des
 */
#define LP_AONCLKRST_LP_CLK_CALI_XTAL_FORCE_ON    (BIT(29))
#define LP_AONCLKRST_LP_CLK_CALI_XTAL_FORCE_ON_M  (LP_AONCLKRST_LP_CLK_CALI_XTAL_FORCE_ON_V << LP_AONCLKRST_LP_CLK_CALI_XTAL_FORCE_ON_S)
#define LP_AONCLKRST_LP_CLK_CALI_XTAL_FORCE_ON_V  0x00000001U
#define LP_AONCLKRST_LP_CLK_CALI_XTAL_FORCE_ON_S  29
/** LP_AONCLKRST_LP_CLK_CALI_FOSC_RST_EN : R/W; bitpos: [30]; default: 0;
 *  need_des
 */
#define LP_AONCLKRST_LP_CLK_CALI_FOSC_RST_EN    (BIT(30))
#define LP_AONCLKRST_LP_CLK_CALI_FOSC_RST_EN_M  (LP_AONCLKRST_LP_CLK_CALI_FOSC_RST_EN_V << LP_AONCLKRST_LP_CLK_CALI_FOSC_RST_EN_S)
#define LP_AONCLKRST_LP_CLK_CALI_FOSC_RST_EN_V  0x00000001U
#define LP_AONCLKRST_LP_CLK_CALI_FOSC_RST_EN_S  30
/** LP_AONCLKRST_LP_CLK_CALI_SOSC_RST_EN : R/W; bitpos: [31]; default: 0;
 *  need_des
 */
#define LP_AONCLKRST_LP_CLK_CALI_SOSC_RST_EN    (BIT(31))
#define LP_AONCLKRST_LP_CLK_CALI_SOSC_RST_EN_M  (LP_AONCLKRST_LP_CLK_CALI_SOSC_RST_EN_V << LP_AONCLKRST_LP_CLK_CALI_SOSC_RST_EN_S)
#define LP_AONCLKRST_LP_CLK_CALI_SOSC_RST_EN_V  0x00000001U
#define LP_AONCLKRST_LP_CLK_CALI_SOSC_RST_EN_S  31

/** LP_AONCLKRST_ANAPERI_REG register
 *  need_des
 */
#define LP_AONCLKRST_ANAPERI_REG (DR_REG_LP_AONCLKRST_BASE + 0x18)
/** LP_AONCLKRST_LP_ANAPERI_RST_EN : R/W; bitpos: [31]; default: 0;
 *  need_des
 */
#define LP_AONCLKRST_LP_ANAPERI_RST_EN    (BIT(31))
#define LP_AONCLKRST_LP_ANAPERI_RST_EN_M  (LP_AONCLKRST_LP_ANAPERI_RST_EN_V << LP_AONCLKRST_LP_ANAPERI_RST_EN_S)
#define LP_AONCLKRST_LP_ANAPERI_RST_EN_V  0x00000001U
#define LP_AONCLKRST_LP_ANAPERI_RST_EN_S  31

/** LP_AONCLKRST_HUK_REG register
 *  need_des
 */
#define LP_AONCLKRST_HUK_REG (DR_REG_LP_AONCLKRST_BASE + 0x1c)
/** LP_AONCLKRST_LP_HUK_RST_EN : R/W; bitpos: [31]; default: 0;
 *  need_des
 */
#define LP_AONCLKRST_LP_HUK_RST_EN    (BIT(31))
#define LP_AONCLKRST_LP_HUK_RST_EN_M  (LP_AONCLKRST_LP_HUK_RST_EN_V << LP_AONCLKRST_LP_HUK_RST_EN_S)
#define LP_AONCLKRST_LP_HUK_RST_EN_V  0x00000001U
#define LP_AONCLKRST_LP_HUK_RST_EN_S  31

/** LP_AONCLKRST_FOSC_DFREQ_REG register
 *  need_des
 */
#define LP_AONCLKRST_FOSC_DFREQ_REG (DR_REG_LP_AONCLKRST_BASE + 0x20)
/** LP_AONCLKRST_FOSC_DFREQ : R/W; bitpos: [31:22]; default: 261;
 *  need_des
 */
#define LP_AONCLKRST_FOSC_DFREQ    0x000003FFU
#define LP_AONCLKRST_FOSC_DFREQ_M  (LP_AONCLKRST_FOSC_DFREQ_V << LP_AONCLKRST_FOSC_DFREQ_S)
#define LP_AONCLKRST_FOSC_DFREQ_V  0x000003FFU
#define LP_AONCLKRST_FOSC_DFREQ_S  22

/** LP_AONCLKRST_RC32K_DFREQ_REG register
 *  need_des
 */
#define LP_AONCLKRST_RC32K_DFREQ_REG (DR_REG_LP_AONCLKRST_BASE + 0x24)
/** LP_AONCLKRST_RC32K_DFREQ : R/W; bitpos: [31:0]; default: 650;
 *  need_des
 */
#define LP_AONCLKRST_RC32K_DFREQ    0xFFFFFFFFU
#define LP_AONCLKRST_RC32K_DFREQ_M  (LP_AONCLKRST_RC32K_DFREQ_V << LP_AONCLKRST_RC32K_DFREQ_S)
#define LP_AONCLKRST_RC32K_DFREQ_V  0xFFFFFFFFU
#define LP_AONCLKRST_RC32K_DFREQ_S  0

/** LP_AONCLKRST_SOSC_DFREQ_REG register
 *  need_des
 */
#define LP_AONCLKRST_SOSC_DFREQ_REG (DR_REG_LP_AONCLKRST_BASE + 0x28)
/** LP_AONCLKRST_SOSC_DFREQ : R/W; bitpos: [31:22]; default: 172;
 *  need_des
 */
#define LP_AONCLKRST_SOSC_DFREQ    0x000003FFU
#define LP_AONCLKRST_SOSC_DFREQ_M  (LP_AONCLKRST_SOSC_DFREQ_V << LP_AONCLKRST_SOSC_DFREQ_S)
#define LP_AONCLKRST_SOSC_DFREQ_V  0x000003FFU
#define LP_AONCLKRST_SOSC_DFREQ_S  22

/** LP_AONCLKRST_XTAL32K_REG register
 *  need_des
 */
#define LP_AONCLKRST_XTAL32K_REG (DR_REG_LP_AONCLKRST_BASE + 0x2c)
/** LP_AONCLKRST_DRES_XTAL32K : R/W; bitpos: [24:22]; default: 3;
 *  need_des
 */
#define LP_AONCLKRST_DRES_XTAL32K    0x00000007U
#define LP_AONCLKRST_DRES_XTAL32K_M  (LP_AONCLKRST_DRES_XTAL32K_V << LP_AONCLKRST_DRES_XTAL32K_S)
#define LP_AONCLKRST_DRES_XTAL32K_V  0x00000007U
#define LP_AONCLKRST_DRES_XTAL32K_S  22
/** LP_AONCLKRST_DGM_XTAL32K : R/W; bitpos: [27:25]; default: 3;
 *  need_des
 */
#define LP_AONCLKRST_DGM_XTAL32K    0x00000007U
#define LP_AONCLKRST_DGM_XTAL32K_M  (LP_AONCLKRST_DGM_XTAL32K_V << LP_AONCLKRST_DGM_XTAL32K_S)
#define LP_AONCLKRST_DGM_XTAL32K_V  0x00000007U
#define LP_AONCLKRST_DGM_XTAL32K_S  25
/** LP_AONCLKRST_DBUF_XTAL32K : R/W; bitpos: [28]; default: 0;
 *  need_des
 */
#define LP_AONCLKRST_DBUF_XTAL32K    (BIT(28))
#define LP_AONCLKRST_DBUF_XTAL32K_M  (LP_AONCLKRST_DBUF_XTAL32K_V << LP_AONCLKRST_DBUF_XTAL32K_S)
#define LP_AONCLKRST_DBUF_XTAL32K_V  0x00000001U
#define LP_AONCLKRST_DBUF_XTAL32K_S  28
/** LP_AONCLKRST_DAC_XTAL32K : R/W; bitpos: [31:29]; default: 3;
 *  need_des
 */
#define LP_AONCLKRST_DAC_XTAL32K    0x00000007U
#define LP_AONCLKRST_DAC_XTAL32K_M  (LP_AONCLKRST_DAC_XTAL32K_V << LP_AONCLKRST_DAC_XTAL32K_S)
#define LP_AONCLKRST_DAC_XTAL32K_V  0x00000007U
#define LP_AONCLKRST_DAC_XTAL32K_S  29

/** LP_AONCLKRST_HPCORE0_RESET_CAUSE_REG register
 *  need_des
 */
#define LP_AONCLKRST_HPCORE0_RESET_CAUSE_REG (DR_REG_LP_AONCLKRST_BASE + 0x30)
/** LP_AONCLKRST_HPCORE0_RESET_FLAG : RO; bitpos: [0]; default: 0;
 *  need_des
 */
#define LP_AONCLKRST_HPCORE0_RESET_FLAG    (BIT(0))
#define LP_AONCLKRST_HPCORE0_RESET_FLAG_M  (LP_AONCLKRST_HPCORE0_RESET_FLAG_V << LP_AONCLKRST_HPCORE0_RESET_FLAG_S)
#define LP_AONCLKRST_HPCORE0_RESET_FLAG_V  0x00000001U
#define LP_AONCLKRST_HPCORE0_RESET_FLAG_S  0
/** LP_AONCLKRST_HPCORE0_RESET_CAUSE : RO; bitpos: [6:1]; default: 0;
 *  6'h1: POR reset
 *  6'h3: digital system software reset
 *  6'h5: PMU HP system power down reset
 *  6'h7: HP system reset from HP watchdog0
 *  6'h8: HP system reset from HP watchdog1
 *  6'h9: HP system reset from LP watchdog
 *  6'hb: HP core reset from HP watchdog
 *  6'hc: HP core software reset
 *  6'hd: HP core reset from LP watchdog
 *  6'hf: brown out reset
 *  6'h10: LP watchdog chip reset
 *  6'h12: super watch dog reset
 *  6'h13: glitch reset
 *  6'h14: efuse crc error reset
 *  6'h16: HP usb jtag chip reset
 *  6'h17: HP usb uart chip reset
 *  6'h18: HP jtag reset
 *  6'h1a: HP core lockup
 */
#define LP_AONCLKRST_HPCORE0_RESET_CAUSE    0x0000003FU
#define LP_AONCLKRST_HPCORE0_RESET_CAUSE_M  (LP_AONCLKRST_HPCORE0_RESET_CAUSE_V << LP_AONCLKRST_HPCORE0_RESET_CAUSE_S)
#define LP_AONCLKRST_HPCORE0_RESET_CAUSE_V  0x0000003FU
#define LP_AONCLKRST_HPCORE0_RESET_CAUSE_S  1
/** LP_AONCLKRST_HPCORE0_RESET_CAUSE_CLR : WT; bitpos: [30]; default: 0;
 *  need_des
 */
#define LP_AONCLKRST_HPCORE0_RESET_CAUSE_CLR    (BIT(30))
#define LP_AONCLKRST_HPCORE0_RESET_CAUSE_CLR_M  (LP_AONCLKRST_HPCORE0_RESET_CAUSE_CLR_V << LP_AONCLKRST_HPCORE0_RESET_CAUSE_CLR_S)
#define LP_AONCLKRST_HPCORE0_RESET_CAUSE_CLR_V  0x00000001U
#define LP_AONCLKRST_HPCORE0_RESET_CAUSE_CLR_S  30
/** LP_AONCLKRST_HPCORE0_RESET_FLAG_CLR : WT; bitpos: [31]; default: 0;
 *  need_des
 */
#define LP_AONCLKRST_HPCORE0_RESET_FLAG_CLR    (BIT(31))
#define LP_AONCLKRST_HPCORE0_RESET_FLAG_CLR_M  (LP_AONCLKRST_HPCORE0_RESET_FLAG_CLR_V << LP_AONCLKRST_HPCORE0_RESET_FLAG_CLR_S)
#define LP_AONCLKRST_HPCORE0_RESET_FLAG_CLR_V  0x00000001U
#define LP_AONCLKRST_HPCORE0_RESET_FLAG_CLR_S  31

/** LP_AONCLKRST_HPCORE1_RESET_CAUSE_REG register
 *  need_des
 */
#define LP_AONCLKRST_HPCORE1_RESET_CAUSE_REG (DR_REG_LP_AONCLKRST_BASE + 0x34)
/** LP_AONCLKRST_HPCORE1_RESET_FLAG : RO; bitpos: [0]; default: 0;
 *  need_des
 */
#define LP_AONCLKRST_HPCORE1_RESET_FLAG    (BIT(0))
#define LP_AONCLKRST_HPCORE1_RESET_FLAG_M  (LP_AONCLKRST_HPCORE1_RESET_FLAG_V << LP_AONCLKRST_HPCORE1_RESET_FLAG_S)
#define LP_AONCLKRST_HPCORE1_RESET_FLAG_V  0x00000001U
#define LP_AONCLKRST_HPCORE1_RESET_FLAG_S  0
/** LP_AONCLKRST_HPCORE1_RESET_CAUSE : RO; bitpos: [6:1]; default: 0;
 *  6'h1: POR reset
 *  6'h3: digital system software reset
 *  6'h5: PMU HP system power down reset
 *  6'h7: HP system reset from HP watchdog0
 *  6'h8: HP system reset from HP watchdog1
 *  6'h9: HP system reset from LP watchdog
 *  6'hb: HP core reset from HP watchdog
 *  6'hc: HP core software reset
 *  6'hd: HP core reset from LP watchdog
 *  6'hf: brown out reset
 *  6'h10: LP watchdog chip reset
 *  6'h12: super watch dog reset
 *  6'h13: glitch reset
 *  6'h14: efuse crc error reset
 *  6'h16: HP usb jtag chip reset
 *  6'h17: HP usb uart chip reset
 *  6'h18: HP jtag reset
 *  6'h1a: HP core lockup
 */
#define LP_AONCLKRST_HPCORE1_RESET_CAUSE    0x0000003FU
#define LP_AONCLKRST_HPCORE1_RESET_CAUSE_M  (LP_AONCLKRST_HPCORE1_RESET_CAUSE_V << LP_AONCLKRST_HPCORE1_RESET_CAUSE_S)
#define LP_AONCLKRST_HPCORE1_RESET_CAUSE_V  0x0000003FU
#define LP_AONCLKRST_HPCORE1_RESET_CAUSE_S  1
/** LP_AONCLKRST_HPCORE1_RESET_CAUSE_CLR : WT; bitpos: [30]; default: 0;
 *  need_des
 */
#define LP_AONCLKRST_HPCORE1_RESET_CAUSE_CLR    (BIT(30))
#define LP_AONCLKRST_HPCORE1_RESET_CAUSE_CLR_M  (LP_AONCLKRST_HPCORE1_RESET_CAUSE_CLR_V << LP_AONCLKRST_HPCORE1_RESET_CAUSE_CLR_S)
#define LP_AONCLKRST_HPCORE1_RESET_CAUSE_CLR_V  0x00000001U
#define LP_AONCLKRST_HPCORE1_RESET_CAUSE_CLR_S  30
/** LP_AONCLKRST_HPCORE1_RESET_FLAG_CLR : WT; bitpos: [31]; default: 0;
 *  need_des
 */
#define LP_AONCLKRST_HPCORE1_RESET_FLAG_CLR    (BIT(31))
#define LP_AONCLKRST_HPCORE1_RESET_FLAG_CLR_M  (LP_AONCLKRST_HPCORE1_RESET_FLAG_CLR_V << LP_AONCLKRST_HPCORE1_RESET_FLAG_CLR_S)
#define LP_AONCLKRST_HPCORE1_RESET_FLAG_CLR_V  0x00000001U
#define LP_AONCLKRST_HPCORE1_RESET_FLAG_CLR_S  31

/** LP_AONCLKRST_LPCORE_RESET_CAUSE_REG register
 *  need_des
 */
#define LP_AONCLKRST_LPCORE_RESET_CAUSE_REG (DR_REG_LP_AONCLKRST_BASE + 0x38)
/** LP_AONCLKRST_LPCORE_RESET_FLAG : RO; bitpos: [0]; default: 0;
 *  need_des
 */
#define LP_AONCLKRST_LPCORE_RESET_FLAG    (BIT(0))
#define LP_AONCLKRST_LPCORE_RESET_FLAG_M  (LP_AONCLKRST_LPCORE_RESET_FLAG_V << LP_AONCLKRST_LPCORE_RESET_FLAG_S)
#define LP_AONCLKRST_LPCORE_RESET_FLAG_V  0x00000001U
#define LP_AONCLKRST_LPCORE_RESET_FLAG_S  0
/** LP_AONCLKRST_LPCORE_RESET_CAUSE : RO; bitpos: [6:1]; default: 0;
 *  6'h1: POR reset
 *  6'h9: PMU LP PERI power down reset
 *  6'ha: PMU LP CPU reset
 *  6'hf: brown out reset
 *  6'h10: LP watchdog chip reset
 *  6'h12: super watch dog reset
 *  6'h13: glitch reset
 *  6'h14: software reset
 */
#define LP_AONCLKRST_LPCORE_RESET_CAUSE    0x0000003FU
#define LP_AONCLKRST_LPCORE_RESET_CAUSE_M  (LP_AONCLKRST_LPCORE_RESET_CAUSE_V << LP_AONCLKRST_LPCORE_RESET_CAUSE_S)
#define LP_AONCLKRST_LPCORE_RESET_CAUSE_V  0x0000003FU
#define LP_AONCLKRST_LPCORE_RESET_CAUSE_S  1
/** LP_AONCLKRST_LPCORE_RESET_CAUSE_PMU_LP_CPU_MASK : R/W; bitpos: [29]; default: 1;
 *  1'b0: enable lpcore pmu_lp_cpu_reset reset_cause, 1'b1: disable lpcore
 *  pmu_lp_cpu_reset reset_cause
 */
#define LP_AONCLKRST_LPCORE_RESET_CAUSE_PMU_LP_CPU_MASK    (BIT(29))
#define LP_AONCLKRST_LPCORE_RESET_CAUSE_PMU_LP_CPU_MASK_M  (LP_AONCLKRST_LPCORE_RESET_CAUSE_PMU_LP_CPU_MASK_V << LP_AONCLKRST_LPCORE_RESET_CAUSE_PMU_LP_CPU_MASK_S)
#define LP_AONCLKRST_LPCORE_RESET_CAUSE_PMU_LP_CPU_MASK_V  0x00000001U
#define LP_AONCLKRST_LPCORE_RESET_CAUSE_PMU_LP_CPU_MASK_S  29
/** LP_AONCLKRST_LPCORE_RESET_CAUSE_CLR : WT; bitpos: [30]; default: 0;
 *  need_des
 */
#define LP_AONCLKRST_LPCORE_RESET_CAUSE_CLR    (BIT(30))
#define LP_AONCLKRST_LPCORE_RESET_CAUSE_CLR_M  (LP_AONCLKRST_LPCORE_RESET_CAUSE_CLR_V << LP_AONCLKRST_LPCORE_RESET_CAUSE_CLR_S)
#define LP_AONCLKRST_LPCORE_RESET_CAUSE_CLR_V  0x00000001U
#define LP_AONCLKRST_LPCORE_RESET_CAUSE_CLR_S  30
/** LP_AONCLKRST_LPCORE_RESET_FLAG_CLR : WT; bitpos: [31]; default: 0;
 *  need_des
 */
#define LP_AONCLKRST_LPCORE_RESET_FLAG_CLR    (BIT(31))
#define LP_AONCLKRST_LPCORE_RESET_FLAG_CLR_M  (LP_AONCLKRST_LPCORE_RESET_FLAG_CLR_V << LP_AONCLKRST_LPCORE_RESET_FLAG_CLR_S)
#define LP_AONCLKRST_LPCORE_RESET_FLAG_CLR_V  0x00000001U
#define LP_AONCLKRST_LPCORE_RESET_FLAG_CLR_S  31

/** LP_AONCLKRST_HPCORE0_RESET_CTRL_REG register
 *  need_des
 */
#define LP_AONCLKRST_HPCORE0_RESET_CTRL_REG (DR_REG_LP_AONCLKRST_BASE + 0x3c)
/** LP_AONCLKRST_HPCORE0_SW_STALL_CODE : R/W; bitpos: [7:0]; default: 0;
 *  reserved
 */
#define LP_AONCLKRST_HPCORE0_SW_STALL_CODE    0x000000FFU
#define LP_AONCLKRST_HPCORE0_SW_STALL_CODE_M  (LP_AONCLKRST_HPCORE0_SW_STALL_CODE_V << LP_AONCLKRST_HPCORE0_SW_STALL_CODE_S)
#define LP_AONCLKRST_HPCORE0_SW_STALL_CODE_V  0x000000FFU
#define LP_AONCLKRST_HPCORE0_SW_STALL_CODE_S  0
/** LP_AONCLKRST_HPCORE0_STALL_WAIT : R/W; bitpos: [14:8]; default: 0;
 *  need_des
 */
#define LP_AONCLKRST_HPCORE0_STALL_WAIT    0x0000007FU
#define LP_AONCLKRST_HPCORE0_STALL_WAIT_M  (LP_AONCLKRST_HPCORE0_STALL_WAIT_V << LP_AONCLKRST_HPCORE0_STALL_WAIT_S)
#define LP_AONCLKRST_HPCORE0_STALL_WAIT_V  0x0000007FU
#define LP_AONCLKRST_HPCORE0_STALL_WAIT_S  8
/** LP_AONCLKRST_HPCORE0_STALL_EN : R/W; bitpos: [15]; default: 0;
 *  need_des
 */
#define LP_AONCLKRST_HPCORE0_STALL_EN    (BIT(15))
#define LP_AONCLKRST_HPCORE0_STALL_EN_M  (LP_AONCLKRST_HPCORE0_STALL_EN_V << LP_AONCLKRST_HPCORE0_STALL_EN_S)
#define LP_AONCLKRST_HPCORE0_STALL_EN_V  0x00000001U
#define LP_AONCLKRST_HPCORE0_STALL_EN_S  15
/** LP_AONCLKRST_HPCORE0_RESET_LENGTH : R/W; bitpos: [18:16]; default: 1;
 *  need_des
 */
#define LP_AONCLKRST_HPCORE0_RESET_LENGTH    0x00000007U
#define LP_AONCLKRST_HPCORE0_RESET_LENGTH_M  (LP_AONCLKRST_HPCORE0_RESET_LENGTH_V << LP_AONCLKRST_HPCORE0_RESET_LENGTH_S)
#define LP_AONCLKRST_HPCORE0_RESET_LENGTH_V  0x00000007U
#define LP_AONCLKRST_HPCORE0_RESET_LENGTH_S  16
/** LP_AONCLKRST_HPCORE0_ENABLE_LP_WDT_RESET : R/W; bitpos: [19]; default: 0;
 *  write 1 to enable lp_wdt reset hpcore0 feature, write 0 to disable lp_wdt reset
 *  hpcore0 feature
 */
#define LP_AONCLKRST_HPCORE0_ENABLE_LP_WDT_RESET    (BIT(19))
#define LP_AONCLKRST_HPCORE0_ENABLE_LP_WDT_RESET_M  (LP_AONCLKRST_HPCORE0_ENABLE_LP_WDT_RESET_V << LP_AONCLKRST_HPCORE0_ENABLE_LP_WDT_RESET_S)
#define LP_AONCLKRST_HPCORE0_ENABLE_LP_WDT_RESET_V  0x00000001U
#define LP_AONCLKRST_HPCORE0_ENABLE_LP_WDT_RESET_S  19
/** LP_AONCLKRST_HPCORE0_SW_RESET : WT; bitpos: [20]; default: 0;
 *  need_des
 */
#define LP_AONCLKRST_HPCORE0_SW_RESET    (BIT(20))
#define LP_AONCLKRST_HPCORE0_SW_RESET_M  (LP_AONCLKRST_HPCORE0_SW_RESET_V << LP_AONCLKRST_HPCORE0_SW_RESET_S)
#define LP_AONCLKRST_HPCORE0_SW_RESET_V  0x00000001U
#define LP_AONCLKRST_HPCORE0_SW_RESET_S  20
/** LP_AONCLKRST_HPCORE0_OCD_HALT_ON_RESET : R/W; bitpos: [29]; default: 0;
 *  need_des
 */
#define LP_AONCLKRST_HPCORE0_OCD_HALT_ON_RESET    (BIT(29))
#define LP_AONCLKRST_HPCORE0_OCD_HALT_ON_RESET_M  (LP_AONCLKRST_HPCORE0_OCD_HALT_ON_RESET_V << LP_AONCLKRST_HPCORE0_OCD_HALT_ON_RESET_S)
#define LP_AONCLKRST_HPCORE0_OCD_HALT_ON_RESET_V  0x00000001U
#define LP_AONCLKRST_HPCORE0_OCD_HALT_ON_RESET_S  29
/** LP_AONCLKRST_HPCORE0_STAT_VECTOR_SEL : R/W; bitpos: [30]; default: 1;
 *  1'b1: boot from HP TCM ROM: 0x4FC00000
 *  1'b0: boot from LP TCM RAM:  0x50108000
 */
#define LP_AONCLKRST_HPCORE0_STAT_VECTOR_SEL    (BIT(30))
#define LP_AONCLKRST_HPCORE0_STAT_VECTOR_SEL_M  (LP_AONCLKRST_HPCORE0_STAT_VECTOR_SEL_V << LP_AONCLKRST_HPCORE0_STAT_VECTOR_SEL_S)
#define LP_AONCLKRST_HPCORE0_STAT_VECTOR_SEL_V  0x00000001U
#define LP_AONCLKRST_HPCORE0_STAT_VECTOR_SEL_S  30
/** LP_AONCLKRST_HPCORE0_LOCKUP_RESET_EN : R/W; bitpos: [31]; default: 0;
 *  write 1 to enable hpcore0 lockup reset feature, write 0 to disable hpcore0 lockup
 *  reset feature
 */
#define LP_AONCLKRST_HPCORE0_LOCKUP_RESET_EN    (BIT(31))
#define LP_AONCLKRST_HPCORE0_LOCKUP_RESET_EN_M  (LP_AONCLKRST_HPCORE0_LOCKUP_RESET_EN_V << LP_AONCLKRST_HPCORE0_LOCKUP_RESET_EN_S)
#define LP_AONCLKRST_HPCORE0_LOCKUP_RESET_EN_V  0x00000001U
#define LP_AONCLKRST_HPCORE0_LOCKUP_RESET_EN_S  31

/** LP_AONCLKRST_HPCORE1_RESET_CTRL_REG register
 *  need_des
 */
#define LP_AONCLKRST_HPCORE1_RESET_CTRL_REG (DR_REG_LP_AONCLKRST_BASE + 0x40)
/** LP_AONCLKRST_HPCORE1_SW_STALL_CODE : R/W; bitpos: [7:0]; default: 0;
 *  reserved
 */
#define LP_AONCLKRST_HPCORE1_SW_STALL_CODE    0x000000FFU
#define LP_AONCLKRST_HPCORE1_SW_STALL_CODE_M  (LP_AONCLKRST_HPCORE1_SW_STALL_CODE_V << LP_AONCLKRST_HPCORE1_SW_STALL_CODE_S)
#define LP_AONCLKRST_HPCORE1_SW_STALL_CODE_V  0x000000FFU
#define LP_AONCLKRST_HPCORE1_SW_STALL_CODE_S  0
/** LP_AONCLKRST_HPCORE1_STALL_WAIT : R/W; bitpos: [14:8]; default: 0;
 *  need_des
 */
#define LP_AONCLKRST_HPCORE1_STALL_WAIT    0x0000007FU
#define LP_AONCLKRST_HPCORE1_STALL_WAIT_M  (LP_AONCLKRST_HPCORE1_STALL_WAIT_V << LP_AONCLKRST_HPCORE1_STALL_WAIT_S)
#define LP_AONCLKRST_HPCORE1_STALL_WAIT_V  0x0000007FU
#define LP_AONCLKRST_HPCORE1_STALL_WAIT_S  8
/** LP_AONCLKRST_HPCORE1_STALL_EN : R/W; bitpos: [15]; default: 0;
 *  need_des
 */
#define LP_AONCLKRST_HPCORE1_STALL_EN    (BIT(15))
#define LP_AONCLKRST_HPCORE1_STALL_EN_M  (LP_AONCLKRST_HPCORE1_STALL_EN_V << LP_AONCLKRST_HPCORE1_STALL_EN_S)
#define LP_AONCLKRST_HPCORE1_STALL_EN_V  0x00000001U
#define LP_AONCLKRST_HPCORE1_STALL_EN_S  15
/** LP_AONCLKRST_HPCORE1_RESET_LENGTH : R/W; bitpos: [18:16]; default: 1;
 *  need_des
 */
#define LP_AONCLKRST_HPCORE1_RESET_LENGTH    0x00000007U
#define LP_AONCLKRST_HPCORE1_RESET_LENGTH_M  (LP_AONCLKRST_HPCORE1_RESET_LENGTH_V << LP_AONCLKRST_HPCORE1_RESET_LENGTH_S)
#define LP_AONCLKRST_HPCORE1_RESET_LENGTH_V  0x00000007U
#define LP_AONCLKRST_HPCORE1_RESET_LENGTH_S  16
/** LP_AONCLKRST_HPCORE1_ENABLE_LP_WDT_RESET : R/W; bitpos: [19]; default: 0;
 *  write 1 to enable lp_wdt reset hpcore1 feature, write 0 to disable lp_wdt reset
 *  hpcore1 feature
 */
#define LP_AONCLKRST_HPCORE1_ENABLE_LP_WDT_RESET    (BIT(19))
#define LP_AONCLKRST_HPCORE1_ENABLE_LP_WDT_RESET_M  (LP_AONCLKRST_HPCORE1_ENABLE_LP_WDT_RESET_V << LP_AONCLKRST_HPCORE1_ENABLE_LP_WDT_RESET_S)
#define LP_AONCLKRST_HPCORE1_ENABLE_LP_WDT_RESET_V  0x00000001U
#define LP_AONCLKRST_HPCORE1_ENABLE_LP_WDT_RESET_S  19
/** LP_AONCLKRST_HPCORE1_SW_RESET : WT; bitpos: [20]; default: 0;
 *  need_des
 */
#define LP_AONCLKRST_HPCORE1_SW_RESET    (BIT(20))
#define LP_AONCLKRST_HPCORE1_SW_RESET_M  (LP_AONCLKRST_HPCORE1_SW_RESET_V << LP_AONCLKRST_HPCORE1_SW_RESET_S)
#define LP_AONCLKRST_HPCORE1_SW_RESET_V  0x00000001U
#define LP_AONCLKRST_HPCORE1_SW_RESET_S  20
/** LP_AONCLKRST_HPCORE1_OCD_HALT_ON_RESET : R/W; bitpos: [29]; default: 0;
 *  need_des
 */
#define LP_AONCLKRST_HPCORE1_OCD_HALT_ON_RESET    (BIT(29))
#define LP_AONCLKRST_HPCORE1_OCD_HALT_ON_RESET_M  (LP_AONCLKRST_HPCORE1_OCD_HALT_ON_RESET_V << LP_AONCLKRST_HPCORE1_OCD_HALT_ON_RESET_S)
#define LP_AONCLKRST_HPCORE1_OCD_HALT_ON_RESET_V  0x00000001U
#define LP_AONCLKRST_HPCORE1_OCD_HALT_ON_RESET_S  29
/** LP_AONCLKRST_HPCORE1_STAT_VECTOR_SEL : R/W; bitpos: [30]; default: 1;
 *  1'b1: boot from HP TCM ROM: 0x4FC00000
 *  1'b0: boot from LP TCM RAM:  0x50108000
 */
#define LP_AONCLKRST_HPCORE1_STAT_VECTOR_SEL    (BIT(30))
#define LP_AONCLKRST_HPCORE1_STAT_VECTOR_SEL_M  (LP_AONCLKRST_HPCORE1_STAT_VECTOR_SEL_V << LP_AONCLKRST_HPCORE1_STAT_VECTOR_SEL_S)
#define LP_AONCLKRST_HPCORE1_STAT_VECTOR_SEL_V  0x00000001U
#define LP_AONCLKRST_HPCORE1_STAT_VECTOR_SEL_S  30
/** LP_AONCLKRST_HPCORE1_LOCKUP_RESET_EN : R/W; bitpos: [31]; default: 0;
 *  write 1 to enable hpcore1 lockup reset feature, write 0 to disable hpcore1 lockup
 *  reset feature
 */
#define LP_AONCLKRST_HPCORE1_LOCKUP_RESET_EN    (BIT(31))
#define LP_AONCLKRST_HPCORE1_LOCKUP_RESET_EN_M  (LP_AONCLKRST_HPCORE1_LOCKUP_RESET_EN_V << LP_AONCLKRST_HPCORE1_LOCKUP_RESET_EN_S)
#define LP_AONCLKRST_HPCORE1_LOCKUP_RESET_EN_V  0x00000001U
#define LP_AONCLKRST_HPCORE1_LOCKUP_RESET_EN_S  31

/** LP_AONCLKRST_TOUCH_AON_REG register
 *  need_des
 */
#define LP_AONCLKRST_TOUCH_AON_REG (DR_REG_LP_AONCLKRST_BASE + 0x44)
/** LP_AONCLKRST_TOUCH_AON_RST_EN : R/W; bitpos: [31]; default: 0;
 *  need_des
 */
#define LP_AONCLKRST_TOUCH_AON_RST_EN    (BIT(31))
#define LP_AONCLKRST_TOUCH_AON_RST_EN_M  (LP_AONCLKRST_TOUCH_AON_RST_EN_V << LP_AONCLKRST_TOUCH_AON_RST_EN_S)
#define LP_AONCLKRST_TOUCH_AON_RST_EN_V  0x00000001U
#define LP_AONCLKRST_TOUCH_AON_RST_EN_S  31

/** LP_AONCLKRST_HP_CLK_CTRL_REG register
 *  HP Clock Control Register.
 */
#define LP_AONCLKRST_HP_CLK_CTRL_REG (DR_REG_LP_AONCLKRST_BASE + 0x48)
/** LP_AONCLKRST_CLK_XTAL_FREQ : RO; bitpos: [6:0]; default: 40;
 *  XTAL Clock Freq Indication. 7'd40: xtal_40m, 7'd48: xtal_48m
 */
#define LP_AONCLKRST_CLK_XTAL_FREQ    0x0000007FU
#define LP_AONCLKRST_CLK_XTAL_FREQ_M  (LP_AONCLKRST_CLK_XTAL_FREQ_V << LP_AONCLKRST_CLK_XTAL_FREQ_S)
#define LP_AONCLKRST_CLK_XTAL_FREQ_V  0x0000007FU
#define LP_AONCLKRST_CLK_XTAL_FREQ_S  0

/** LP_AONCLKRST_CPLL_DIV_REG register
 *  need_des
 */
#define LP_AONCLKRST_CPLL_DIV_REG (DR_REG_LP_AONCLKRST_BASE + 0x4c)
/** LP_AONCLKRST_CPLL_REF_DIV : R/W; bitpos: [3:0]; default: 2;
 *  cpll ref div value
 */
#define LP_AONCLKRST_CPLL_REF_DIV    0x0000000FU
#define LP_AONCLKRST_CPLL_REF_DIV_M  (LP_AONCLKRST_CPLL_REF_DIV_V << LP_AONCLKRST_CPLL_REF_DIV_S)
#define LP_AONCLKRST_CPLL_REF_DIV_V  0x0000000FU
#define LP_AONCLKRST_CPLL_REF_DIV_S  0
/** LP_AONCLKRST_CPLL_FB_DIV : R/W; bitpos: [11:4]; default: 15;
 *  cpll fb div value
 */
#define LP_AONCLKRST_CPLL_FB_DIV    0x000000FFU
#define LP_AONCLKRST_CPLL_FB_DIV_M  (LP_AONCLKRST_CPLL_FB_DIV_V << LP_AONCLKRST_CPLL_FB_DIV_S)
#define LP_AONCLKRST_CPLL_FB_DIV_V  0x000000FFU
#define LP_AONCLKRST_CPLL_FB_DIV_S  4

/** LP_AONCLKRST_APLL_DIV_REG register
 *  need_des
 */
#define LP_AONCLKRST_APLL_DIV_REG (DR_REG_LP_AONCLKRST_BASE + 0x50)
/** LP_AONCLKRST_APLL_REF_DIV : R/W; bitpos: [2:0]; default: 5;
 *  apll ref div value
 */
#define LP_AONCLKRST_APLL_REF_DIV    0x00000007U
#define LP_AONCLKRST_APLL_REF_DIV_M  (LP_AONCLKRST_APLL_REF_DIV_V << LP_AONCLKRST_APLL_REF_DIV_S)
#define LP_AONCLKRST_APLL_REF_DIV_V  0x00000007U
#define LP_AONCLKRST_APLL_REF_DIV_S  0
/** LP_AONCLKRST_APLL_OUT_DIV : R/W; bitpos: [7:3]; default: 16;
 *  apll out div value
 */
#define LP_AONCLKRST_APLL_OUT_DIV    0x0000001FU
#define LP_AONCLKRST_APLL_OUT_DIV_M  (LP_AONCLKRST_APLL_OUT_DIV_V << LP_AONCLKRST_APLL_OUT_DIV_S)
#define LP_AONCLKRST_APLL_OUT_DIV_V  0x0000001FU
#define LP_AONCLKRST_APLL_OUT_DIV_S  3

/** LP_AONCLKRST_MSPI_DIV_REG register
 *  need_des
 */
#define LP_AONCLKRST_MSPI_DIV_REG (DR_REG_LP_AONCLKRST_BASE + 0x54)
/** LP_AONCLKRST_MSPI_REF_DIV : R/W; bitpos: [2:0]; default: 1;
 *  MSPI ref div value
 */
#define LP_AONCLKRST_MSPI_REF_DIV    0x00000007U
#define LP_AONCLKRST_MSPI_REF_DIV_M  (LP_AONCLKRST_MSPI_REF_DIV_V << LP_AONCLKRST_MSPI_REF_DIV_S)
#define LP_AONCLKRST_MSPI_REF_DIV_V  0x00000007U
#define LP_AONCLKRST_MSPI_REF_DIV_S  0
/** LP_AONCLKRST_MSPI_FB_DIV : R/W; bitpos: [7:3]; default: 24;
 *  MSPI fb div value
 */
#define LP_AONCLKRST_MSPI_FB_DIV    0x0000001FU
#define LP_AONCLKRST_MSPI_FB_DIV_M  (LP_AONCLKRST_MSPI_FB_DIV_V << LP_AONCLKRST_MSPI_FB_DIV_S)
#define LP_AONCLKRST_MSPI_FB_DIV_V  0x0000001FU
#define LP_AONCLKRST_MSPI_FB_DIV_S  3
/** LP_AONCLKRST_MSPI_CHGP_DCUR : R/W; bitpos: [8]; default: 0;
 *  MSPI chgp_dcur value
 */
#define LP_AONCLKRST_MSPI_CHGP_DCUR    (BIT(8))
#define LP_AONCLKRST_MSPI_CHGP_DCUR_M  (LP_AONCLKRST_MSPI_CHGP_DCUR_V << LP_AONCLKRST_MSPI_CHGP_DCUR_S)
#define LP_AONCLKRST_MSPI_CHGP_DCUR_V  0x00000001U
#define LP_AONCLKRST_MSPI_CHGP_DCUR_S  8
/** LP_AONCLKRST_MSPI_LF_RES : R/W; bitpos: [9]; default: 0;
 *  MSPI lf_res value
 */
#define LP_AONCLKRST_MSPI_LF_RES    (BIT(9))
#define LP_AONCLKRST_MSPI_LF_RES_M  (LP_AONCLKRST_MSPI_LF_RES_V << LP_AONCLKRST_MSPI_LF_RES_S)
#define LP_AONCLKRST_MSPI_LF_RES_V  0x00000001U
#define LP_AONCLKRST_MSPI_LF_RES_S  9

/** LP_AONCLKRST_LP_ADI_REG register
 *  need_des
 */
#define LP_AONCLKRST_LP_ADI_REG (DR_REG_LP_AONCLKRST_BASE + 0x58)
/** LP_AONCLKRST_LP_ADI_RST_EN : R/W; bitpos: [31]; default: 0;
 *  need_des
 */
#define LP_AONCLKRST_LP_ADI_RST_EN    (BIT(31))
#define LP_AONCLKRST_LP_ADI_RST_EN_M  (LP_AONCLKRST_LP_ADI_RST_EN_V << LP_AONCLKRST_LP_ADI_RST_EN_S)
#define LP_AONCLKRST_LP_ADI_RST_EN_V  0x00000001U
#define LP_AONCLKRST_LP_ADI_RST_EN_S  31

/** LP_AONCLKRST_LPROOT_CLK_DIV_REG register
 *  need_des
 */
#define LP_AONCLKRST_LPROOT_CLK_DIV_REG (DR_REG_LP_AONCLKRST_BASE + 0x5c)
/** LP_AONCLKRST_LPAON_CLK_DIV_NUM : R/W; bitpos: [2:0]; default: 0;
 *  lp aon clock divide num
 */
#define LP_AONCLKRST_LPAON_CLK_DIV_NUM    0x00000007U
#define LP_AONCLKRST_LPAON_CLK_DIV_NUM_M  (LP_AONCLKRST_LPAON_CLK_DIV_NUM_V << LP_AONCLKRST_LPAON_CLK_DIV_NUM_S)
#define LP_AONCLKRST_LPAON_CLK_DIV_NUM_V  0x00000007U
#define LP_AONCLKRST_LPAON_CLK_DIV_NUM_S  0
/** LP_AONCLKRST_LPPERI_CLK_DIV_NUM : R/W; bitpos: [6:4]; default: 0;
 *  lp peri clock divide num
 */
#define LP_AONCLKRST_LPPERI_CLK_DIV_NUM    0x00000007U
#define LP_AONCLKRST_LPPERI_CLK_DIV_NUM_M  (LP_AONCLKRST_LPPERI_CLK_DIV_NUM_V << LP_AONCLKRST_LPPERI_CLK_DIV_NUM_S)
#define LP_AONCLKRST_LPPERI_CLK_DIV_NUM_V  0x00000007U
#define LP_AONCLKRST_LPPERI_CLK_DIV_NUM_S  4

/** LP_AONCLKRST_CPLL_CFG_REG register
 *  need_des
 */
#define LP_AONCLKRST_CPLL_CFG_REG (DR_REG_LP_AONCLKRST_BASE + 0x60)
/** LP_AONCLKRST_CPLL_DBIAS : R/W; bitpos: [2:0]; default: 0;
 *  cpll dbias value
 */
#define LP_AONCLKRST_CPLL_DBIAS    0x00000007U
#define LP_AONCLKRST_CPLL_DBIAS_M  (LP_AONCLKRST_CPLL_DBIAS_V << LP_AONCLKRST_CPLL_DBIAS_S)
#define LP_AONCLKRST_CPLL_DBIAS_V  0x00000007U
#define LP_AONCLKRST_CPLL_DBIAS_S  0
/** LP_AONCLKRST_CPLL_DCHGP : R/W; bitpos: [5:3]; default: 0;
 *  cpll dchgp value
 */
#define LP_AONCLKRST_CPLL_DCHGP    0x00000007U
#define LP_AONCLKRST_CPLL_DCHGP_M  (LP_AONCLKRST_CPLL_DCHGP_V << LP_AONCLKRST_CPLL_DCHGP_S)
#define LP_AONCLKRST_CPLL_DCHGP_V  0x00000007U
#define LP_AONCLKRST_CPLL_DCHGP_S  3
/** LP_AONCLKRST_CPLL_DR1 : R/W; bitpos: [8:6]; default: 0;
 *  cpll dr1 value
 */
#define LP_AONCLKRST_CPLL_DR1    0x00000007U
#define LP_AONCLKRST_CPLL_DR1_M  (LP_AONCLKRST_CPLL_DR1_V << LP_AONCLKRST_CPLL_DR1_S)
#define LP_AONCLKRST_CPLL_DR1_V  0x00000007U
#define LP_AONCLKRST_CPLL_DR1_S  6
/** LP_AONCLKRST_CPLL_DR3 : R/W; bitpos: [11:9]; default: 0;
 *  cpll dr3 value
 */
#define LP_AONCLKRST_CPLL_DR3    0x00000007U
#define LP_AONCLKRST_CPLL_DR3_M  (LP_AONCLKRST_CPLL_DR3_V << LP_AONCLKRST_CPLL_DR3_S)
#define LP_AONCLKRST_CPLL_DR3_V  0x00000007U
#define LP_AONCLKRST_CPLL_DR3_S  9

/** LP_AONCLKRST_APLL_SDM_REG register
 *  need_des
 */
#define LP_AONCLKRST_APLL_SDM_REG (DR_REG_LP_AONCLKRST_BASE + 0x64)
/** LP_AONCLKRST_APLL_SDM : R/W; bitpos: [21:0]; default: 0;
 *  apll sdm value
 */
#define LP_AONCLKRST_APLL_SDM    0x003FFFFFU
#define LP_AONCLKRST_APLL_SDM_M  (LP_AONCLKRST_APLL_SDM_V << LP_AONCLKRST_APLL_SDM_S)
#define LP_AONCLKRST_APLL_SDM_V  0x003FFFFFU
#define LP_AONCLKRST_APLL_SDM_S  0

/** LP_AONCLKRST_RTC_SAR2_PWDET_CCT_REG register
 *  need_des
 */
#define LP_AONCLKRST_RTC_SAR2_PWDET_CCT_REG (DR_REG_LP_AONCLKRST_BASE + 0x68)
/** LP_AONCLKRST_RTC_SAR2_PWDET_CCT : R/W; bitpos: [2:0]; default: 0;
 *  rtc_sar2_pwdet_cct value
 */
#define LP_AONCLKRST_RTC_SAR2_PWDET_CCT    0x00000007U
#define LP_AONCLKRST_RTC_SAR2_PWDET_CCT_M  (LP_AONCLKRST_RTC_SAR2_PWDET_CCT_V << LP_AONCLKRST_RTC_SAR2_PWDET_CCT_S)
#define LP_AONCLKRST_RTC_SAR2_PWDET_CCT_V  0x00000007U
#define LP_AONCLKRST_RTC_SAR2_PWDET_CCT_S  0

/** LP_AONCLKRST_DATE_REG register
 *  need_des
 */
#define LP_AONCLKRST_DATE_REG (DR_REG_LP_AONCLKRST_BASE + 0x3fc)
/** LP_AONCLKRST_DATE : R/W; bitpos: [30:0]; default: 38826752;
 *  need_des
 */
#define LP_AONCLKRST_DATE    0x7FFFFFFFU
#define LP_AONCLKRST_DATE_M  (LP_AONCLKRST_DATE_V << LP_AONCLKRST_DATE_S)
#define LP_AONCLKRST_DATE_V  0x7FFFFFFFU
#define LP_AONCLKRST_DATE_S  0
/** LP_AONCLKRST_CLK_EN : R/W; bitpos: [31]; default: 0;
 *  need_des
 */
#define LP_AONCLKRST_CLK_EN    (BIT(31))
#define LP_AONCLKRST_CLK_EN_M  (LP_AONCLKRST_CLK_EN_V << LP_AONCLKRST_CLK_EN_S)
#define LP_AONCLKRST_CLK_EN_V  0x00000001U
#define LP_AONCLKRST_CLK_EN_S  31

#ifdef __cplusplus
}
#endif
